Updated: avril 27, 2011
This page collects all informations on how to use PREEMPT-RT soft realtime extension with the Altera NIOS II softcore processor. We have made an effort to propose this new port. With codesign, a new difficulty appears with flexibility during codesign generation. This page proposes to give important informations specially to this important part. Our wish is that your experience on PREEMPT-RT for NIOS II will be successful!
You need a board with an Altera FPGA circuit and a system (JTAG) for programming it. We suggest to use:
This is a quick and dirty tutorial:
You must have a design for NIOS II with MMU enabled. You must verify that you can boot a standard Linux kernel first on your board. Please follow this documentation.
We have added the hrtimer support. So you must in your SoPC builder design add a full featured 64-bit timer named hrclock.
You must have finally 2 timers:
Please respect the name of the timers...
It was difficult to synchronize the Linux kernel version for NIOS II with the PREEMPT-RT patch version for the vanilla Linux kernel. We have decided to start from the vanilla Linux kernel instead from the Linux kernel for NIOS II...
1. Download the Linux distribution for NIOS II (if not):
$ cd $ wget http://www.niosftp.com/pub/linux/nios2-linux-20090929.tar
$ tar xf nios2-linux-20090929.tar
$ cd nios2-linux
$ ./checkout $ ./update
Download the vanilla Linux kernel version 220.127.116.11:
. Download the vanilla Linux kernel version 18.104.22.168:
$ cd $ wget ftp://ftp.kernel.org/pub/linux/kernel/v2.6/linux-22.214.171.124.tar.bz2 $ tar -xvjf linux-126.96.36.199.tar.bz2
3. Apply the general PREEMPT-RT patch version 188.8.131.52-rt27.:
$ cd $ wget http://www.kernel.org/pub/linux/kernel/projects/rt/older/patch-184.108.40.206-rt27.bz2 $ cd linux-220.127.116.11 $ bzcat ../patch-18.104.22.168-rt27.bz2 | patch -p
the particular PREEMPT-RT patch version 22.214.171.124-rt27-nios2-1.0-00 for NIOS
4. Apply the particular PREEMPT-RT patch version 126.96.36.199-rt27-nios2-1.0-00 for NIOS II:
$ cd $ wget http://uuu.enseirb-matmeca.fr/~kadionik/nios2-preempt-rt/patchs/preempt-rt-188.8.131.52-rt27-nios2-1.0-00.patch $ cd linux-184.108.40.206 $ patch -p1 <../preempt-rt-220.127.116.11-rt27-nios2-1.0-00.patch
5. Replace the linux-2.6 directory from nios2-linux directory by the patched linux-18.104.22.168 directory:
$ cd $ cd nios2-linux/ $ mv linux-2.6 linux-2.6.org $ mv ../linux-22.214.171.124 linux-2.6
6. Configure the kernel to use the PREEMPT-RT preemption mode with high resolution timer support enabled and download finally the image into your board.
This initial port gives some extra latency with some boards. The cache size, MMU parameters and SoPC design have directly influence on latency.
We have detected extra latency of up to 1500 µs with a Stratix 1S10 board with a dd stressing. The NIOS II processor used in this design has just 512B On-Chip Memory, 8kB Instruction Master Cache and 4kB Data Master Cache.
We have just latency of up to 650 µs with a Cyclone 3C120 board with a dd stressing. The NIOS II processor used in this design has 1024B On-Chip Memory, 32kB Instruction Master Cache and 32kB Data Master Cache.
The Linux port for NIOS II may surely be improved for reducing latency (arch/nios2/kernel/entry.S file).
This port is surely perfectible. If you make improvements, you may contact us...
Latency can be measured with classical tools provided through cross compilation. The principe is to generate a periodic thread and to measure difference between the effectiv period and the theorical period that defines latency.
For stressing the system, we have used:
The realtime group scheduling must be inhibited:
# echo -1 > /proc/sys/kernel/sched_rt_runtime_us
For measuring latencies, boards are stressed by stress tool (# stress -c 50 -i 50 &) and ping flooding (# ping -f @IP).
Linux kernel version
Max latency (1)
NIOS II Frequency
MMU and Cache Configuration
|Altera Stratix 1S10 board||126.96.36.199||188.8.131.52-rt27||
||Patrice Kadionik||08/16/2010 trace||From Altera standard reference design|
|Altera Cyclone III 3C25 board||184.108.40.206||220.127.116.11-rt27||
||Patrice Kadionik||08/16/2010 trace||From Altera standard_neek_80 reference design|
|Altera Cyclone III 3C120 board||18.104.22.168||22.214.171.124-rt27||
||Patrice Kadionik||02/15/2011 trace||From Altera Altera_NiosII_Linux_Deliverables reference design|
The following Altera SoPC designs for PREEMPT-RT are given as an example without any guaranty and AS IS. You must purchase Altera tools for regenerating files for programming your Altera FPGA of your board.